Switched-capacitor techniques have been used to implement a wide variety of circuits. Classes of circuits that utilize these techniques include digital-to-analog converter (DAC) and analog to-digital converter (ADC) circuits. Many architectures exist for implementing both ADCs and DACs. One popular architecture is a pipeline ADC architecture. In a pipeline ADC, a plurality of pipeline stages are connected in series, and each stage converts an analog input signal to a corresponding digital output signal at an associated digital resolution. All but the last stage also reconvert the digital output to a corresponding analog output, and subtract the analog output from the analog input to generate an analog residue. An amplified version of this residue is fed to the next stage as its analog input. The digital outputs from all of the stages are combined to provide an overall digital output.
One implementation of a pipeline ADC involves using a switched-capacitor multiplying DAC (MDAC) to perform both the digital-to-analog reconversion and the subtraction of the resulting analog output from the analog input in a given pipeline stage. The MDAC typically samples the analog input signal during a first phase of a multi-phase clocking scheme, and then subtracts the analog output signal from the analog input signal during a second phase of the clocking scheme. The sampling of the analog input, and the subsequent generation and subtraction of the analog output from the analog input, can be accomplished using either the same or different capacitors in the MDAC. Efficiencies can be achieved by using the same capacitors to implement both of these functions, such as achieving an increased feedback factor, which in turn results in reduced noise, non-linearities, and circuit area.
However, the use of the same capacitors in the MDAC to accomplish both the sampling of the input signal and the generation and subtraction of the analog output from the analog input may also result in problems. Using the same set of capacitors in this way may result in a common mode voltage level change, also referred to as a common mode “hop,” appearing at certain nodes of the circuit. For example, to sample the input signal, it may typically be applied to terminals of capacitors during the first active phase, and to generate and subtract the analog output signal from the analog input signal, selected reference voltages may be applied to these same terminals during the second active phase, based on the digital output generated by that stage. The sampled input signal and the selected reference voltages typically have different common mode values. As a result of the switched-capacitor nature of the circuit operation, this common mode voltage difference may result in movement of a common mode voltage appearing at an input of an amplifier of the MDAC. However, MDAC amplifiers often have stringent performance requirements, which translate into a relatively small preferred input common mode voltage ranges. Any deviation from this preferred common mode input range, such as due to an unfettered common mode hop, may undesirably reduce performance or increase design specifications of the MDAC and corresponding pipeline ADC.
Therefore, a need exists for switched capacitor circuits, including to implement MDACs for use in pipelined ADCs, that can utilize a common set of capacitors for multiple functions, such as for both sampling of an analog input signal and generation and subtraction of an analog output signal from the analog input signal, without incurring an undesirable common-mode voltages at the input of an amplifier of the switched-capacitor circuit.